The present invention relates to a method of manufacturing a trench MOSFET, and more particularly to a method of manufacturing a trench MOSFET with high cell density.
Presently, products of power MOSFETs tend to have two features of low on-resistance (Rds-on) and high switch speed for improving the practical applications. The feature of low Rds-on is relative to the cell pitch and the cell density of the memory units in a device. Hence, the cell pitch of the memory units tends to decrease for increasing the cell density, thereby approaching the feature of low Rds-on. In order to decrease the cell pitch of the memory units, the designed pitch should be decreased. However the minimum pitch is limited due to the present producing equipments.
The traditional methods of manufacturing a trench MOSFET are disclosed in U.S. Pat. Nos. 5,567,634, 5,665,619, 5,904,525, 6,312,993, 6,368,920 and so on, which are incorporated herein by reference.
FIGS. 1(a)-1(k) schematically illustrate a traditional method of manufacturing a trench MOSFET. Firstly, an epitaxy layer 12 is formed on a substrate 11 and then a mask oxide layer 13 is formed on the epitaxy layer 12, as shown in FIG. 1(a). A photoresist 14 is formed on the mask oxide layer 13 and then a lithography and etching process is executed to define a trench opening on the mask oxide layer 13, as shown in FIG. 1(b). Subsequently, the photoresist 14 is removed and a dry etching process is executed to form a trench structure on the epitaxy layer 12, as shown in FIG. 1(c). Afterward, the mask oxide layer 13 is removed, as shown in FIG. 1(d). Further, a gate oxide layer 15 is formed on the surface of the epitaxy layer 12 and the inner sidewall of the trench structure, and then a polysilicon layer 16 is filled into the trench structure by deposition/lithography/etching process, as shown in FIG. 1(e). Then, a body implantation process is performed to form and drive in a body structure 121 in the epitaxy layer 12, as shown in FIG. 1(f). Subsequently, a photoresist 17 is formed on the above structure and defined by a lithography and etching process to form a source photoresist for a follow-up source structure, as shown in FIG. 1(g). Then a source implantation process is performed to form a source layer 122 in the body structure 121, and then the photoresist 17 is removed to complete a source structure drive-in, as shown in FIG. 1(h).
Afterward, a borophosphosilicate glass (BPSG) oxide layer 18 is deposited on the above structure and planarized to be a dielectric layer, and then a photoresist 19 for defining a contact region is formed on the BPSG oxide layer 18, as shown in FIG. 1(i). Subsequently, an etching process is performed to remove a portion of the BPSG oxide layer 18 for forming the contact region contacting with the source structure 122, and then a contact plus implantation process is performed to form the contact structure 123 in the body structure 121 after the photoresist 19 is removed, as shown in FIG. 1(j). Finally, a conductive metal layer 20 is sputtered on the above structure and then a lithography and etching process is performed to form the trench MOSFET, as shown in FIG. 1(k).
In the field of semiconductor manufacture technology, however, when a trench MOSFET or a shallow trench isolation (STI) structure is manufactured, the opening width of the trench is limited by the resolution of lithography process. Therefore the dimension of the entire device cannot be decreased as desired. Moreover, taking the above-described method for example, when the cell pitch of memory units is decreased, the introduced photoresist 17 may peel off during the ion implantation process (step (g) described above), which results a failure of the device. On the other hand, when the contact region is defined, the source structure 122 will be etched and removed partially, as shown in FIG. 1(j). Accordingly, when the contact region is filled with AlSiCu, it is easy to form poor metal step coverage between the conductive metal layer 20 and the source structure 122, thereby influencing the electrical performance of the entire device.